This file lists all important changes to ATS9350 Firmware
[21.13] - 2017-09-01
- Added support for a 200KHz ADC plugged into the Master/Slave connector. 12 bit data is reported in footer bits 15..4. Presence of the module is reported in Reg_02. Footer signature is 0x01 if the add-on module is plugged in.
[21.08] - 2017-02-13
- Added dependency on DUAL_CH_MODE for TRIG_PER_TRIGEN when using the 31 bit Trig per Trig En.
[21.07] - 2016-12-02
- Changed MS_TRIGGERo to come out of a ddio block and changed MS_TRIG_OUT to have a clock enable to give 2 clock delay for SyncBoard 4X-W. Was giving a trigger jitter before.
[21.06] - 2016-06-30
- Added logic to reset MPFE memory when SD_INIT (Reg_01 = 0-1-0) is issued. SD_INIT also aborts any ongoing captures to make sure memory test does not fail.
[21.05] - 2016-06-03
- Used FFT v4.7 that does faster zero padding.
- Also increased clock frequency to 420 MHz.
- Needs driver/dll v5.10.11+ otherwise every other buffer is missed in FFT mode.
[21.04] - 2016-01-13
- Added BUFFER_DONE signal to stall DMA circuit between engine switch.
[21.02] - 2015-12-17
- Fixed the polarity of SLOW_EXTCLK_EN for calculating ALLOW_TRIGGER. This should eliminate the garbage data at the start of record in NPT Pretrig.
[21.01] - 2015-12-08
- Uses FFT 3.15 engine.
- Added NPT footers for FFT (time domain & freq domain).
- Added OCT Ignore Bad Clock.
- Increased NPT rec length counter to 28 bits (512M in dual & 1G in single).
- Had to add FFT data mux after FFT as FFT 3.15 does not support pass thru mode.
[20.11] - 2014-06-16
- Optimized PCIe settings to improve signal integrity.
[20.08] - 2014-01-28
- Changed DSP_CLK to be 210 MHz, so 100 KHz FFTs can be done safely.
[20.00] - 2014-01-16
[18.15] - 2013-10-25
- Added logic to delay READ_FINISHED_LCLK until C2S_LAST_POINT in continuous mode if READ_FINISHED_LCK was going to occur while OPEN_FLOODGATES was still HIGH. This fixes a problem in dual CPU systems (e.g. Dell T7600) that pause their dma response for some reason.
[18.14] - 2013-02-13
- Added logic to handle different X and Y slopes for external trigger.
[18.11] - 2012-07-17
- Added reset to MPFE when Reg_01 (aka CLR_MT_FIFO) is set to '1'.
[18.10] - 2012-06-28
- Pacer output can be made undisturbed by setting bit 31 of pacer value = '1'.
[18.09] - 2012-06-19
- Changed NPT mode pretrigger value in Streaming Fifo.bdf to not be dependent on SHARED_MEMORY. This will fix the single channel pre-trig bug.