This file lists all important changes to ATS9130 Firmware
[5.14] - 2019-12-09
Fixed bug in FIFO Overflow logic that was causing overflows to not be reported.
Added Slow External Clock support by connecting the signal to the correct place in the logic.
Added special feature that allows user to capture one sample per external trigger by setting REG_06[21..30] = '11'.
Added "open floodgates" at the end of acquisition if USE_FPGA_FIFO is '1'.
[5.07] - 2018-11-26